(DSDL5) Arithmetic Addition

module adder4(carryin, x0, x1, x2, x3, y0, y1, y2, y3, s0, s1, s2, s3, carryout);
    input carryin, x3, x2, x1, x0, y3, y2, y1, y0;
    output s0, s1, s2, s3, carryout;
    fulladd stage0 (carryin, x0, y0, s0, c1);
    fulladd stage1 (c1, x1, y1, s1, c2);
    fulladd stage2 (c2, x2, y2, s2, c3);
    fulladd stage3 (c3, x3, y3, s3, carryout);
endmodule

module fulladd(carryin, x, y, s, carryout);
    input carryin, x, y;
    output s, carryout;
    assign s = x ^ y ^ carryin;
    assign carryout = (x & y) | (x & carryin) | (y & carryin);
endmodule