(DSDL8) Comparators

Verilog Code

module comparator (
    input a,
    input b,
    output reg equal,
    output reg lower,
    output reg greater
    );
    always @(a or b)
      if (a<b) begin
        equal = 0;
        lower = 1;
        greater = 0;
      end
      else if (a==b) begin
        equal = 1;
        lower = 0;
        greater = 0;
      end
      else begin
        equal = 0;
        lower = 0;
        greater = 1;
      end
endmodule

Waveform

Schematic