(DSDL9) Full Adder VHDL Forms

Verilog Code

DATAFLOW Form

module fullAdder(
	input a, b, c_in,
	output sum, c_out
);
	assign sum = a ^ b ^ c_in;
	assign c_out = (a & b) | (a & c_in) | (b & c_in);
endmodule

Behavorial Form

module fulladder(abc, sum, carry
	input [2:0] abc,
	output reg sum, carry
);
	always@(abc) begin
		case (abc)
			3’b000: begin sum=1’b0; carry=1’b0; end
			3’b001: begin sum=1’b1; carry=1’b0; end
			3’b010: begin sum=1’b1; carry=1’b0; end
			3’b011: begin sum=1’b0; carry=1’b1; end
			3’b100: begin sum=1’b1; carry=1’b0; end
			3’b101: begin sum=1’b0; carry=1’b1; end
			3’b110: begin sum=1’b0; carry=1’b1; end
			3’b111: begin sum=1’b1; carry=1’b1; end
		endcase
	end
endmodule

Structural Form

module fullAdder(
	input a, b, c_in,
	output sum, c_out
);
	wire temp1, temp2, temp3;
	halfAdder HA1 (a, b, temp1, temp2);
	halfAdder HA2 (c_in, temp1, sum, temp3);
	assign c_out = temp3 | temp2;
endmodule

module halfAdder(
	input a, b,
	output s, c
);
	assign s = a ^ b;
	assign c = a & b;
endmodule

Waveform

Schematic